Typically, a BJT consists of a vertical stack of npn or pnp semiconductor materials. A BJT can take the form of a double heterojunction bipolar transistor (DHBT), as compared to a homojunction BJT. High speed operation is achieved through judicious scaling down of the thickness of the vertical stack of semiconductors and scaling down of the lateral dimensions of the size and spacing of the contacts. The electron transit time decreases though device scaling of the vertical and lateral dimensions. Also, the parasitics associated with capacitance increases as the vertical dimensions are reduced. For example, thinning the base and collector layers reduces the carrier transit times but increases the base resistance and base collector capacitance. The base collector capacitance can be reduced through lithographically scaling the base, collector, and emitter regions. However, the parasitics associated with the contact resistance increase as the lateral dimensions are reduced, since resistance is proportional to the contact area.
Vertical scaling of the epitaxial structure and lithographic lateral scaling are the traditional approaches used to improve transistor performance. A cross-sectional view of a conventional Indium Phosphide based DHBT (InP-based DHBT) that utilizes the triple mesa architecture is illustrated in FIG. 1, which depicts the prior art. Here, emitter contact 10, base contacts 20, and collector contact 30 all lie at different vertical positions. There is a base-collector capacitance, Cbc, which includes the base collector capacitance from the intrinsic base (base region located adjacent the emitter in the vertical direction) and the extrinsic base (the base region which extends laterally from the intrinsic base region. The extrinsic base includes the region to which external base contacts 20 are made). As the extrinsic base area is reduced, the capacitance Cbc decreases, but the base contact resistance increases. As such, the conventional mesa structure is not optimal for parasitics reduction due to the following disadvantage: Independent optimization of the extrinsic base contact area and the capacitance Cbc is not possible. Hence there is significant base-collector capacitance which arises from the collector region that lies under the base contact. Additionally, the base contact area cannot be increased without incurring a capacitance Cbc penalty.
In view of the forgoing, the above described traditional BJTs have a base contact area that is coupled to a parasitic base-collector capacitance Cbc, thereby frustrating device scaling. As such, there is a continuing need to reduce the parasitic capacitance and the base resistance of BJTs, thereby enabling operation of the BJTs at higher speed. The present invention addresses this continuing need as well.